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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

38 Freescale Semiconductor

System Design Information

These requirements are shown graphically in Figure 16.

Figure 16. MPC7448 Power Up Sequencing Requirements

Certain stipulations also apply to the manner in which the power rails of the MPC7448 power down, as

follows:

•OV

may ramp down any time before or after V

• The voltage at the SYSCLK input must not exceed V

once V

has ramped down below 0.9 V.

• The voltage at the SYSCLK input must not exceed OV

by more 20% during transients (see

overshoot/undershoot specifications in Figure 2) or 0.3 V DC (see Table 2) at any time.

SYSCLK

0.9 V

no restrictions between

and V

0.9 V

limit imposed by V

if OV

ramps up first

limit imposed by OV

if V

ramps up first

100 μs (nominal) delay from V

to AV

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