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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Freescale Semiconductor 3

Features

2Features

This section summarizes features of the MPC7448 implementation.

Major features of the MPC7448 are as follows:

• High-performance, superscalar microprocessor

— Up to four instructions can be fetched from the instruction cache at a time.

— Up to three instructions plus a branch instruction can be dispatched to the issue queues at a

time.

— Up to 12 instructions can be in the instruction queue (IQ).

— Up to 16 instructions can be at some stage of execution simultaneously.

— Single-cycle execution for most instructions

— One instruction per clock cycle throughput for most instructions

— Seven-stage pipeline control

• Eleven independent execution units and three register files

— Branch processing unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a target

instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can

be made available from the instruction cache. Typically, a fetch that hits the BTIC provides

the first four instructions in the target stream.

– 2048-entry branch history table (BHT) with 2 bits per entry for four levels of

prediction—not taken, strongly not taken, taken, and strongly taken

– Up to three outstanding speculative branches

– Branch instructions that do not update the count register (CTR) or link register (LR) are

often removed from the instruction stream.

– Eight-entry link register stack to predict the target address of Branch Conditional to Link

— Four integer units (IUs) that share 32 GPRs for integer operands

– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions.

– IU2 executes miscellaneous instructions, including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions.

— Five-stage FPU and 32-entry FPR file

– Fully IEEE Std. 754™-1985–compliant FPU for both single- and double-precision

operations

– Supports non-IEEE mode for time-critical operations

– Hardware support for denormalized numbers

– Thirty-two 64-bit FPRs for single- or double-precision operands

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