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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor 19

Electrical and Thermal Characteristics

5.2.3 IEEE 1149.1 AC Timing Specifications

Table 10 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 16 through

Figure 19.

Figure 7

provides the AC test load for TDO and the boundary-scan outputs of the MPC7447A.

Figure 7. Alternate AC Test Load for the JTAG Interface

Table 10. JTAG AC Timing Specifications (Independent of SYSCLK)

At recommended operating conditions. See Table 4.

Parameter Symbol Min Max Unit Notes

TCK frequency of operation f

TCLK

0 33.3 MHz

TCK cycle time t

TCLK

30 — ns

TCK clock pulse width measured at 1.4 V t

JHJL

15 — ns

TCK rise and fall times t

and t

—2ns

TRST

assert time t

TRST

25 — ns 2

Input setup times:

Boundary-scan data

TMS, TDI

DVJH

IVJH

—

ns 3

Input hold times:

Boundary-scan data

TMS, TDI

DXJH

IXJH

—

ns 3

Valid times:

Boundary-scan data

TDO

JLDV

JLOV

ns 4

Output hold times:

Boundary-scan data

TDO

JLDX

JLOX

—

ns 4

TCK to output high impedance:

Boundary-scan data

TDO

JLDZ

JLOZ

ns 4, 5

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load

(see Figure 7). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST

is an asynchronous level sensitive signal. The time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Output

= 50 Ω

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 55 56

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